Digital Timing Macromodeling for VLSI Design Verification

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1Core Metadata

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Digital Timing Macromodeling for VLSI Design Verification
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en
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1/1/2019
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2Content

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Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for perform...

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Last updated
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